There is an increasing demand for miniaturization in the integrated circuits industry. This demand has led to an ever constant reduction in separation between conductive lines (e.g., metal lines) in order to reduce integrated circuit size and/or increase density. The reduced spacing between the conductive lines has the undesirable effect of increasing the capacitance of whatever material lies between the conductive lines. This phenomenon is known as capacitive crosstalk.
In the past, overall integrated circuit (IC) performance depended primarily on device properties, however, this is no longer the case. Parasitic resistance, capacitance and inductance associated with interconnections and contacts of an IC are beginning to become increasingly significant factors in IC performance. In current IC technology, the speed limiting factor is no longer device delay, but the resistive-capacitive (RC) delays associated with the conductive interconnections (e.g., metal lines) of the IC.
Conventional ICs typically employ an interconnect structure wherein a first conductive line is adjacent a second conductive line. If the crosstalk or capacitance between the first conductive line and the second conductive line is high, then the voltage on the first conductive line alters or affects the voltage on the second conductive line. This alteration in voltage may result in the IC being inoperable as a result of misinterpreting logic zeros, logic ones and voltage levels, and consequently incorrectly processing binary and/or analog information
In order to reduce capacitive coupling and therefore reduce capacitive crosstalk, low dielectric constant (low-K) materials have been developed to replace conventional dielectric/insulation materials that lie between conductive lines in order to insulate one conductive line from the other. Conventional insulation materials such as silicon dioxide exhibit a dielectric constant of about 4.0. Newer materials with lower dielectric constants have been developed. For example, polyimides generally exhibit a dielectric constant of about 2.4 to about 3.0; Teflon exhibits a dielectric constant of about 1.6 to 2.2; and acrogels typically exhibit a dielectric constant of about 2. However, the use of many low-K dielectric/insulation materials is not practicable because equipment is not available to properly process the new dielectric/insulation materials in various ICs. Furthermore, the chemical or physical properties of many low-K dielectric/insulation materials are usually difficult to make compatible or integrate into conventional IC processing. For example, as multiple layers of interconnects are formed, many low dielectric constant materials used to insulate conductive lines exhibit cracking.
FIGS. 1 and 2 illustrate the relationship between closely spaced conductive lines and capacitive coupling. Conductive lines 30 are adjacent each other and provide necessary electrical connections between devices of an integrated circuit (not shown). Although only three conductive lines 30 are shown for ease of understanding, it is to be appreciated that many thousands or even millions more such conductive lines may exist in the integrated circuit. As noted above, the increasing demand for miniaturization in the integrated circuits industry has led to an ever constant reduction in separation between the conductive lines 30 in order to reduce integrated circuit size. However, the reduced spacing between the conductive lines 30 has the undesirable effect of increasing the capacitance of whatever material lies between the conductive lines 30 to result in capacitive crosstalk between adjacent conductive lines.
A quantity known as pitch (pitch=w+s) is often employed to characterize conductive capacitance crosstalk for adjacent conductive lines used in the integrated circuit industry, where "w" is the cross-sectional width of a conductive line and "s" is the distance of separation between adjacent conductive lines. FIG. 2 graphically illustrates the capacitance between the conductive lines 30 as a function of physical separation. A reduction in pitch is an ongoing activity in the integrated circuit industry in order to optimize substrate surface area utilization in integrated circuits. The capacitance between the conductive lines 30 labeled C.sub.CL in FIG. 2 is shown to increase exponentially as pitch is reduced or as the conductive lines 30 are brought closer together. The increase in capacitive coupling resulting from the conductive lines 30 being brought closer together contributes to capacitive crosstalk between the adjacent conductive lines 30, respectively.
Since market forces are driving the integrated circuitry towards bringing the conductive lines 30 closer together in order to maximize substrate surface utilization, insulation having low dielectric constant is required between the conductive lines 30 in order isolate the conductive lines 30 from one another and to lower capacitive coupling between the conductive lines 30, respectively, and in turn reduce capacitive crosstalk.
Conventional semiconductors such as for example those fabricated according to the aforementioned method do not provide for sufficient insulation between the conductive lines 30 suitable for overcoming capacitive crosstalk between closely spaced conductive lines, particularly at higher frequencies approaching the gigahertz range.
In view of the above, it would be desirable to have a semiconductor fabrication method which provides for an insulation material between conductive lines having a dielectric constant suitable for attaining higher IC control speed and meet increasing substrate surface utilization requirements. Furthermore, it would be desirable for such a method to also provide for formation of a coaxial interconnect structure so as to further enhance IC functionality.